My Message
Suggestions
Internal storage is popular in high-speed boards, which requires engineers to master PCB internal storage design, and learn to organize and classify variable signals. We get to know topology structure, how to do the layout, how to design the isometric drawing ect. Let’s take examples for DDR3.
Layout：
1. Consider about the maintainability of BGA, the min. trace space around BGA component parts is 5MM, with min. BGA 3mm;2. DFM reliability: Per relative process requirement, the component space must meet the DFM requirement, and we have to consider about the beauty of the overall layout;
3. If it is easy to meet absolute isometric drawing and relative length. We have to care about the length limitation and order requirement;
4. The location of filter capacity and pull-up resistors: the capacity should be close to every PIN, while the capacitors scared around the IC, the resistors should be locate per the requirement, ( the layout length should be no more than 500mil).
Layout：
1. Special impedance control: Single-end 5O ohm, differential 100ohm;
2. Data wire is grouped every 11 pieces（D0~D7,DM0,DQS0+/-）,（D8~D15,DM1,DQS1+/-）the ground plane are considered as reference plane, no other signals inside;
3. Try not to change layers for every signals, especially for data wire, no more than 2vias clock line, the signals space must meet 3W standards.
4. Data trace, impedance control trace, clock trace space should be no less than 15MIL or 3W;
5. All the signal trace should not be separated with complete reference plane, once there is layer change, please pay attention to increase the vias or decoupling capacitors;
6. For Vref power plane, the recommended trace width should be no less than 15mil, and the space is no less than 20 mil for other signal traces.
