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I am looking for some design guidelines (length, width, spacing) for solder thieves which are placed behind trailing pins of wave soldered SOICs. I'd appreciate it if some one could direct me to the appropriate reference. Also, has any one performed any experiments to determine the optimal solder thief design? Thanks for the help.
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David Soares
2017/2/28 15:48:38
Great thanks for your helpful info. Really useful.
Waelson Negreiros
2017/2/28 15:48:38
Bookmarked.Really helpful.
servis.av
2017/2/28 15:48:38
Nice content you’ve posted in here
Jorge Arizaga
2017/2/28 15:48:38
Your post answered my questions. Thanks a lot.